1. Field of Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit. More particularly, the present invention relates to a silicon-on-insulator (SOI) silicon controlled rectifier (SCR) structure and associated electrostatic discharge (ESD) protection circuit.
2. Description of Related Art
The development of silicon-on-insulator (SOI) techniques for fabricating integrated circuit (IC) has been extraordinary in recent years. SOI technique involves embedding an insulation layer within a substrate. The insulation layer extends to a region underneath semiconductor device region so that the resulting structural and physical properties of the devices are greatly improved. In general, an SOI structure has an almost perfect sub-threshold swing, no latch-up, a low off-state leakage, low operating voltage and a high current driving capacity. However, the SOI structure also causes electrostatic discharge (ESD) problems. This is mainly because buried oxide layer (the insulation layer) has a low thermal conductivity and a relatively large floating body effect.
ESD is a leading cause of semiconductor device damages during IC packaging. For a CMOS IC, high voltage ESD may lead to the destruction of the thin gate oxide layer inside a CMOS device. To reduce as much as possible the damages to integrated circuits due to ESD, an ESD protection circuit and an IC circuit chip are often integrated together. The ESD circuit is a type of switch. When an ESD incident occurs, the ESD protection circuit immediately becomes conductive, so that high voltage ESD current will be conducted via the protection circuit to the ground. Ultimately, the intense current will discharge via the ESD protection circuit instead of the IC circuit body. However, if there is no voltage surge in the neighborhood of the IC circuit, the ESD circuit will remain closed so that the IC circuit can operate normally.
In bulk/non-epitaxial CMOS manufacturing, the SCR device generally has a low hold voltage (Vhold is about 1V). When an ESD voltage is generated, power consumed by the SCR device (power ≈IESDxc3x97Vhold) is smaller than other ESD protection circuit devices (such as a diode, MOS, BJT or field oxide device). Hence, an SCR device is capable of withstanding a higher ESD voltage in the same device area.
In sub-micron CMOS fabrication, the switching voltage of an SCR device often exceeds 30V but the breakdown voltage of a sub-micron CMOS device is lower than 20V. Consequently, an SCR device is not a suitable ESD circuit protection device on its own. To serve as an ESD protection, the ESD protection circuit needs to have a supplementary circuit added onto the same silicon chip. In the following, a few conventional ESD protection SCR devices are introduced.
FIG. 1 is a schematic cross-sectional view of a conventional ESD protection SCR device. The circuit shown in FIG. 1 is disclosed in U.S. Pat. No. 5,012,317. The SCR device is built upon a P-type substrate 10. The substrate 10 has an N-type well 12. The N-type well 12 has an N+-doped region 14a and a P+-doped region 14b that serve as a cathode of the SCR device. In addition, the P-type substrate 10 has an N+-doped region 14c and a P+-doped region 14d that serve as an anode of the SCR device. In FIG. 1, the SCR only utilizes the contact junction between the P-type substrate 10 and the N-type well 12 to trigger ESD operation. The SCR device has a relatively high switching voltage (greater than 30V in 0.35 xcexcm CMOS process). Since the device is characterized by having a high switching voltage, additional supplementary circuit would be needed to provide a complete ESD protection circuit.
FIG. 2 is a schematic cross-sectional view of a conventional modified lateral SCR device for protecting circuit against ESD. The modified lateral SCR device is disclosed in U.S. Pat. No. 5,225,702. As shown in FIG. 2, one major modification is the addition of an N+-doped region 24c that extends into a portion of the neighboring P-type substrate 20 and the N-type well 22. Through the N+-doped diffusion region, the switching voltage of the SCR device is lowered to the breakdown voltage (about 12V for 0.35 xcexcm CMOS devices) between the P-type substrate 20 and the N+-doped diffusion region 24c. Ultimately, the SCR device is switched at a lower voltage and damaging current is more rapidly channeled away.
FIG. 3 is a schematic cross-sectional view of a low-voltage-triggered SCR device for protecting against ESD. The design is disclosed in U.S. Pat. No. 5,453,384. As shown in FIG. 3, the device represents a further improvement to the modified SCR device shown in FIG. 2. An NMOS transistor (including a gate 44, a source terminal 38 and a drain terminal 40a) is formed above the P-type substrate 30 and the N+-doped diffusion region 38. With this arrangement, the switching voltage of the SCR device is lowered to the breakdown voltage (about 8V for 0.35 xcexcm CMOS devices) of the NMOS transistor. Hence, switching voltage of the SCR device is further lowered without having to add a supplementary circuit to the silicon chip.
FIG. 4 is a schematic cross-sectional view of a conventional doubly stabilized SCR device and switching circuit structure fabricated on a silicon-on-insulator substrate. The design is disclosed in U.S. Pat. No. 6,015,992. As shown in FIG. 4, the doubly stabilized SCR switching circuit is built above the substrate 50 and the insulation layer 56. With the said structure, the discharging route P-N-P-N (66-54-52-58) of the SCR device is blocked by the insulation layer 80. Therefore, two groups of connecting wires 74 and 72 are added to the structure for connecting the severed P-N-P and N-P-N circuits. However, the SCR structure connected as such does not have a low switching voltage like conventional SCR device. So, it does not provide a good protection for the IC.
Accordingly, one object of the present invention is to provide a silicon-on-insulator (SOI) low-voltage-triggered silicon control rectifier (SCR) structure and associated electrostatic discharge (ESD) protection circuit.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a SOI partially-depleted low-voltage-triggered SCR device structure. The SCR device is built upon a substrate and an insulation layer. The insulation layer can be a buried oxide layer formed over the substrate. A plurality of isolation structures over the insulation layer defines a device region. A first-type well (for example, an N-type well) and a second-type well (for example, a P-type well) are formed over the insulation layer in the device region. The first-type and second-type wells are connected. A first gate is formed over the first-type well and a second gate is formed over the second-type well. The first-type well further includes a first second-type doped region (P-type) and a first first-type doped region (N-type) between the first second-type doped region and the isolation structure adjacent to the first second-type doped region. The first second-type doped region and the first first-type doped region together form an anode of the SOI-SCR device. A second first-type doped region is formed within the first-type well between the first second-type doped region and the first gate structure adjacent to the first second-type doped region. A third first-type doped (N-type) region is formed within the first and the second-type well around their junction between the first and second-type well. The second-type well further includes a second second-type doped (P-type) region and a fourth first-type doped (N-type) region within the second-type well between the second second-type doped region and the second gate structure adjacent to the second second-type doped region. The second second-type doped region and the fourth first-type doped region together form a cathode of the SOI-SCR device structure.
The invention also provides a second partially-depleted SOI low-voltage-triggered SCR device structure. The SCR device is formed over a substrate and an insulation layer. The insulation layer can be a buried oxide layer formed over the substrate. A plurality of isolation structures over the insulation layer defines a device region. A first-type well (for example, an N-type well) and a second-type well (for example, a P-type well) are formed over the insulation layer within the device region. The first-type and the second-type wells are connected. A first gate is formed above the first-type well and a second gate is formed above the second-type well. The first-type well has a first second-type doped region adjacent to the first gate structure and a first first-type doped region formed in the first-type well between the first second-type doped region and the isolation structure adjacent to the first second-type doped region. The first second-type doped region and the first first-type doped region are electrically connected to form an anode of the SOI-SCR device. The second second-type doped region is formed within the first and the second-type well around their junction between the first and the second-type well and in between the first and the second gate. The second first-type doped region is formed within the second-type well. A third second-type doped region is formed within the second-type well between the second first-type doped region and the isolation structure and adjacent to the second first-type doped region. The second first-type doped region and the third second-type doped region are electrically connected together to form a cathode of the SOI-SCR device structure. A fourth second-type doped region is formed within the second-type well between the second first-type doped region and the second gate adjacent to the second first-type doped region.
The invention also provides a third SOI fully-depleted low-voltage-triggered SCR device structure. The SCR device is formed over a substrate and an insulation layer. The insulation layer can be a buried oxide layer formed over the substrate. A plurality of isolation structures over the insulation layer defines a device region. A first-type well (for example, an N-type well) and a second-type well (for example, a P-type well) are formed over the insulation layer within the device region. The first-type and the second-type wells are in contact with each other. A first gate structure is formed above the first-type well and a second gate structure is formed above the second-type well. A first first-type doped region is formed within the first-type well adjacent to a portion of the sidewall of the first gate structure. A portion of a first second-type doped region is formed within the first-type well adjacent to the first first-type doped region. A second first-type doped region is formed within the device region between the first second-type doped region and the isolation structure adjacent to the first-type well. The first second-type doped region and the second first-type doped region are electrically connected together to form an anode of the SOI-SCR device. A third first-type doped region is formed within the first-type and the second-type well. The third first-type doped region is formed close to the junction between the first and the second-type well in-between a portion of the sidewall of the first and the second gate. A second second-type doped region is formed within the device region adjacent to the second-type well. A portion of the fourth first-type doped region is formed within the second-type well between the sidewall of the second second-type doped region and a portion of the sidewall of the second gate structure. The second second-type doped region and the fourth first-type doped region together form a cathode of the SOI-SCR device.
The invention also provides a fourth SOI fully-depleted low-voltage-triggered SCR device structure. The SCR device is formed over a substrate and an insulation layer. The insulation layer can be a buried oxide layer formed over the substrate. A plurality of isolation structures over the insulation layer defines a device region. A first-type well (for example, an N-type well) and a second-type well (for example, a P-type well) are formed over the insulation layer within the device region. The first-type and the second-type wells are in contact with each other. A first gate structure is formed above the first-type well and a second gate structure is formed above the second-type well. A first second-type doped region is formed within the first-type well adjacent to a portion of the sidewall of the first gate structure. A first first-type doped region is formed within the device region between the first second-type doped region and the isolation structure adjacent to the first second-type doped region. The first second-type doped region and the first first-type doped region are electrically connected together to form an anode of the SOI-SCR device. A second second-type doped region is formed within a portion of the first and the second-type well adjacent to the their junction and in-between a portion of the sidewall of the first and the second gate. A third second-type doped region is formed within the second-type well adjacent to a portion of the sidewall of the second gate structure. A second first-type doped region is formed in a portion of the second well adjacent to the third second-type doped region. A fourth second-type doped region is formed within the device region between the second first-type doped region and another isolation structure adjacent to the second-type well. The second first-type doped region and the fourth second-type doped region are electrically connected together to form a cathode of the SOI-SCR device.
This invention also provides an electrostatic discharge (ESD) protection circuit having an silicon-on-insulator (SOI) silicon control rectifier (SCR) device therein. The ESD protection circuit is coupled to an input/output pad and an internal circuit inside a silicon chip. The protection circuit includes an SOI-SCR device and an ESD discharge detection circuit. The SOI-SCR device has a cathode, an anode, a first gate and a second gate. The anode is coupled to the input/output pads and the cathode is coupled to a ground terminal. The ESD detection circuit is coupled to the input/output pad and the ground terminal, respectively. The ESD detection circuit further includes at least two output terminals for connecting with the first and the second gate of the SOI-SCR device, respectively
This invention also provides an alternative electrostatic discharge (ESD) protection circuit having a silicon-on-insulator (SOI) silicon control rectifier (SCR) device therein. The ESD protection circuit is coupled to a first voltage source and a second voltage source. The circuit includes an SOI-SCR device, an ESD detection circuit and a diode series comprising a plurality of serially connected diodes. The SOI-SCR device has a cathode, an anode, a first gate and a second gate. The anode is connected to the first voltage source. The ESD detection circuit at least includes a pair of output terminals connected to the first gate and the second gate of the SCR device, respectively. The anode of the diode series is connected to the cathode of the SCR device while the cathode of the diode series is connected to the second voltage source.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.